Energy Efficient Comparator Design |
Author(s): |
| Pawan Singh Bhadouria , Shri Ram College of Engineering and Managment; Mr.Ashish Duvey, SRCEM |
Keywords: |
| Comparator, High Speed Integrated Circuits, VLSI, Low-Power Design, FPGA |
Abstract |
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The energy efficient computations is the requirement for all portable battery operated devices. Along with the arithmetic operation, comparison is a frequency used operation with the computation. This paper explores the existing magnitude comparator design techniques and proposes a new binary comparator that provides significant reduction in the power and area. The effectiveness of the proposed technique over the existing is evaluated by coding in Verilog, synthesized and simulated on Xilinx tool chain and design metrics are evaluated. The simulation results on FPGA show that the proposed comparator provides more than 19.3% reduction in power over the best-known comparator. |
Other Details |
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Paper ID: IJSRDV8I80109 Published in: Volume : 8, Issue : 8 Publication Date: 01/11/2020 Page(s): 338-341 |
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