Implementation Of a XOR Based Vedic Multiplier For Area, Delay And Power Minimization |
Author(s): |
| Shruthy Bastian , IES College of Engineering, Thrissur, India; Bency Varghese A, IES College of Engineering, Thrissur, India; Rachana M K, IES College of Engineering, Thrissur, India |
Keywords: |
| Low Power, Area Efficient, XOR Based Adder, Carry Select Adder, Vedic Multiplier, VHDL |
Abstract |
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Nowadays, most widely used in different types of processors and other digital circuits are adders. In the VLSI design low power and area efficient high-speed circuits are most substantial area of research. One of the fast adders which has less area and reduced power consumption is Carry Select Adder. In this 32-bit carry select adder has been presented using modified XOR based full adder to reduce circuit complexity, area and delay. The modified full adder design needed only two XOR gates and one multiplexer. The modified 32-bit carry select adder gives better result than conventional carry select adder with respect to area, power consumption and delay. Using this modified 32 bit CSA a Vedic multiplier is developed. The software used is XILINIX ISE simulator. Implemented using VHDL module. |
Other Details |
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Paper ID: IJSRDV9I30120 Published in: Volume : 9, Issue : 3 Publication Date: 01/06/2021 Page(s): 147-151 |
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