DADDA Multiplier Design Using Approximate 4:2 Compressor & Carry Look Ahead Adder

Low-power circuit designs have long been a concern in VLSI design. In high-performance systems, multipliers play a crucial role. Digital signal processing (DSP) and Arithmetic Logic Unit (ALU) systems rely heavily on fast multipliers. The performance of a VLSI circuit design is limited by two key factors: delay and area. The paper focuses on the design of a Dadda multiplier using a 4:2 Compressor. The Dadda Multiplier is a new design that uses an exact 4:2 compressor and a ripple carry adder. A 32-bit Dadda Multiplier is implemented in the proposed system employing an approximate 4:2 compressor and a Carry look ahead adder. The proposed multiplier design and traditional designs are created in Verilog HDL and simulated using the Xilinx ISE 14.2 design tool. The 32-bit Dadda Multiplier vs. other 4, 8, and 16-bit Dadda multipliers With an area of 17504 m2, the comparison study results show a reduction in power usage of roughly 59.5 percent, 54.5 percent, and 14 percent.