Design of Frequency Multiplier at 120 GHz for Sub-Millimeter Wave LO Development

In this paper we report the schematic design, layout and results of a high output power balanced tripler at 120 GHz, in which a pair of UMS BES schottky diode is adopted. The design process involves a systematic study of the various parameters such as anode size, diode doping, circuit configuration, circuit topology etc. Considering the present situation of domestic processing technology, the advantage of balanced tripler is this it cannot require any bias, means the design is a self-bias. Here we use antiparallel configuration of diode pair to design a tripler. This configuration has the distinct advantages that only odd harmonics are generated. So requirement and complexity to design a matching network is decreased in this design. The measured schematic results indicate that the output power is 1 dBm at 120 GHz when driven with 15 dBm at 40 Hz of input power. In general, this tripler has important practical value.