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VLSI Implementation of Digital Filter


Professor Disha Bhosle , Atharva College of Engineering, Mumbai, India; Vikas Anaokar, Atharva College of Engineering, Mumbai, India; Omkar Dixit, Atharva College of Engineering, Mumbai, India; Aditya Trivedi, Atharva College of Engineering, Mumbai, India


VLSI, Digital Filter


Designing digital filters mathematically, and verifying their functions, is a simple task with the help of many available electronics CAD software such as MATLAB. With the growth of Programmable Logic Devices (PLD), and Field Programmable Gate Array (FPGA) devices, implementing hardware digital filters became an easy task. PLD and FPGA implementation approach has both, performance of ASICs and flexibility of software. Hence to learn practically how the digital filters work in a computer based environment and then implementing it on PLDs gives a basic idea of implementing algorithms on circuit design level to enhance the concepts. The designed filter can be used to remove powerline interference from the ECG signal. Power line interference cause uneven spikes at 50/60 Hz frequency and can cause inaccuracy in ECG graphs. Hence, this noise has to be eliminated and can be done through IIR/FIR digital filter.

Other Details

Paper ID: NCTAAP016
Published in: Conference 4 : NCTAA 2016
Publication Date: 29/01/2016
Page(s): 64-66

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